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화웨이, 반도체 설계 혁신으로 미국 제재 극복 목표

Huawei touts chip design breakthrough as answer to US sanctions - Light Reading

2026.05.26 16:00 번역됨
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화웨이의 반도체 설계 혁신은 미국 제재를 우회할 수 있어 장기적인 성장을 이끌어낼 수 있습니다.

핵심 요약

화웨이는 2031년까지 1.4나노미터 칩 생산을 목표로 미국 제재를 우회할 수 있는 새로운 반도체 설계 기술을 개발했습니다.

핵심요약

  • 2031년까지 1.4나노미터 칩 생산 목표
  • 현재 스마트폰은 3나노미터 칩, 노키아 장비는 5나노미터 칩 사용
  • 미국 제재로 TSMC와 삼성에서 단절
  • 새로운 설계 기술로 제재 우회 가능성 제시

도입

화웨이의 새로운 반도체 설계 기술은 미국 제재를 우회할 수 있는 가능성이 있습니다. 이는 반도체 산업의 경쟁 구도와 공급망에 큰 영향을 미칠 수 있으며, 투자자들에게 중요한 시사점을 제공합니다.

본문 1: 반도체 설계 기술의 혁신적 의미

화웨이가 2031년까지 1.4나노미터 칩을 생산할 수 있다면, 이는 현재 3나노미터 칩을 사용하는 스마트폰과 5나노미터 칩을 사용하는 노키아 장비보다 더 고성능의 칩을 생산할 수 있는 기술입니다. 이는 반도체 산업의 경쟁 구도를 완전히 바꿀 수 있는 가능성을 가지고 있습니다. 특히, 미국 제재로 인해 TSMC와 삼성에서 단절된 화웨이는 이 기술을 통해 제재를 우회할 수 있는 가능성이 있습니다. 이는 화웨이의 시장 점유율을 높이고, 반도체 공급망의 다양성을 증가시킬 수 있는 기회로 읽힙니다.

본문 2: 미국 제재의 영향과 화웨이의 대응

미국 제재는 화웨이에게 큰 타격을 주었습니다. TSMC와 삼성에서 단절된 화웨이는 새로운 공급망을 찾아야 했습니다. 그러나 화웨이는 새로운 반도체 설계 기술을 개발함으로써 제재를 우회할 수 있는 가능성을 모색하고 있습니다. 이는 미국 제재가 반도체 산업에 미치는 영향을 보여주며, 기업들이 제재를 극복하기 위해 혁신적인 기술을 개발해야 한다는 점을 강조합니다. 또한, 이는 반도체 산업의 경쟁 구도가 변화할 수 있음을 시사하며, 투자자들에게 새로운 투자 기회를 제공할 수 있습니다.

결론

화웨이의 새로운 반도체 설계 기술은 미국 제재를 우회할 수 있는 가능성이 있으며, 이는 반도체 산업의 경쟁 구도와 공급망에 큰 영향을 미칠 수 있습니다. 향후 화웨이의 기술 개발 동향과 미국 제재의 변화에 주목해야 할 필요가 있습니다. 이 기술이 실제로 상용화되면, 반도체 산업의 경쟁 구도가 완전히 바꿀 수 있는 가능성을 가지고 있습니다.


원문 링크: https://news.google.com/rss/articles/CBMiqwFBVV95cUxQZXFOVHRUSEJwZlNJNm9IZG03YjVOM04xR1BESnhxaEJHTnBUaUxfMXlxVW1lQmhhcW9NaEhOOFNobHhLZVUtYkxfMEtKYURETjFQemJWcjZWTUtQSzhJU2hsODV6QVpfWmhsTlNfVmJMaDdYZDloTnhibU5SZHFfcERkNnVOMnRpMXNRSlluVF9ZRk5WOW80X3B1YjdWVTVBUjVnWjVUT0xsS2c?oc=5

Original Article

Huawei touts chip design breakthrough as answer to US sanctions - Light Reading

China's Huawei is feeling chipper about a new way of designing semiconductors that could free it from the constraints imposed by US restrictions.

Dam an unstoppable river and its surging waters may find an alternative route to the sea. It could be one of the Chinese proverbs so beloved of Huawei, which would undoubtedly smile at the comparison. While the US snoozed on Memorial Day, the Chinese technology vendor was briefing local and foreign press on a new approach to semiconductor design that might allow it to bypass American sanctions and manufacture the most bleeding-edge chips. By 2031, it expects to produce chips as capable as those that are conventionally made with transistor measurements of just 1.4 nanometers (billionths of a meter) – more advanced than anything currently available.

Under the shaky principle of Moore's Law, manufacturers have made chips more powerful by effectively shrinking their transistors so that more can be squeezed into the same area. For the transistor measurements cited by the industry, smaller equals better. Today's most sophisticated smartphones run on 3-nanometer chips. Nokia has for a while advertised mobile network equipment featuring 5-nanometer chips. Outside China, such miniaturization has looked beyond the capability of Chinese chipmakers and off limits to Huawei.

As part of the US sanctions program, companies were forbidden from selling components to Huawei if they relied on American technology or intellectual property. The move cut Huawei off from Taiwan's TSMC, the world's leading chip foundry, as well as Samsung, its closest international rival. Besides sourcing machinery from American firms such as Applied Materials, TSMC is also one of the world's biggest customers of ASML, a Dutch company whose technology investments have allowed it to monopolize a critical chipmaking process called extreme ultraviolet lithography (EUV).

Without EUV, making chips based on 7-nanometer designs is thought to be difficult and potentially uneconomical. Anything smaller is deemed impossible by some experts. China has its own chip foundries, the best known of which is probably the Semiconductor Manufacturing International Corporation (SMIC). Yet the Dutch government prohibits ASML from selling EUV equipment to China.

Perhaps for the first time ever, Huawei has now publicly acknowledged that its EUV blackhole prevents it from doing what it calls "geometric scaling," the shrinkage of transistors, to remain competitive. "Geometric scaling needs the most advanced litho tooling, and is rapidly approaching physical boundaries. For us, these challenges arrived earlier and are tougher," said He Tingbo, the president of Huawei's semiconductor business department, during a Monday speech in Shanghai to the IEEE International Symposium on Circuits and Systems.

"So, if scaling no longer delivers free gains and our litho tooling is restricted, how can we keep our words – delivering better products every year or two?" she continued in her speech, a transcript of which was forwarded to Light Reading by Huawei representatives.

The answer, Huawei believes, lies in allowing chips to execute decisions more quickly by optimizing processes and shortening the distances around the circuit. Instead of shrinking components and laying them out in a line, it would effectively construct towers of circuitry, making a chip look more like a Shanghai skyscraper rather than a street of American bungalows.

"It is built on a brand-new free logic design concept, expanding from a single-layer to a double-layer architecture," explained He. Huawei has christened the new approach "time scaling" and is already showing off an architectural design it has named "LogicFolding." In honor of He's contribution, and a cheeky poke at the rapidly flagging Moore's Law, Huawei cites "Her's Law" in its press release, reflecting the pronunciation of the executive's name.

In the absence of all this, Huawei would appear to be stuck at 7-nanometer designs. As He described it in her speech, "after Kirin 9030Pro launched in 2025, our chips may have reached saturation. It will be very challenging to maintain the same momentum of evolution." Manufactured by SMIC, these Kirin 9030Pro chips are thought by analysts to use an optimized 7-nanometer design process.

SMIC appears to have done that by using an older technology called deep ultraviolet lithography (DUV), the forerunner of EUV. While banned from shipping EUV and more advanced DUV products to China, ASML has been allowed to continue selling its older DUV machines there, and it still counted China as its single biggest market last year, responsible for more than €9.5 billion (US$11.1 billion) of its revenues, roughly 29% of the total.

To produce those optimized 7-nanometer chips, SMIC is believed to have combined DUV technology with multiple patterning, which essentially repeats the lithography process. Experts say this is likely to result in lower yields, measuring the percentage of functional chips. Some doubt it can be done economically.

Even if time scaling and LogicFolding are as good as Huawei boasts, the commercial production in 2031 of chips matching the performance of 1.4-nanometer designs would put the Chinese vendor several years behind the global market. TSMC expects to begin mass production of 1.4-nanometer chips in 2028. Given the pace of development, it could be churning out even more advanced chips three years later.

There is also no guarantee that time scaling and LogicFolding will take off. "After all these practices, we know many challenges remain," acknowledged He in her speech. The "folding" of circuitry into vertical stacks requires production tools that do not currently exist. Energy consumption is another concern, she said, providing a candid assessment of the technology's status today.

Huawei's claims also came without any third-party validation. Some analysts quoted in the mainstream press were dubious while others had little insight to offer that could not be gleaned from studying the speech by He. A shift from purely two-dimensional to more three-dimensional chip designs is not an entirely new concept in the semiconductor industry. That semiconductor giants outside China have had less to say on this topic does not mean they aren't exploring it.

Few would challenge He's assertion that the geometric scaling associated with Moore's Law has started to "slow down." Indeed, none other than Jensen Huang, the boss of the world's biggest semiconductor company, has argued for several years that Moore's Law is dead. For the CEO of Nvidia, the solution is an industry pivot from the central processing units that handle traditional workloads to his more AI-friendly graphics processing units. But a limit to geometric scaling could ultimately hinder Nvidia as much as anyone else.

One mistake made by successive US hawks has been to consistently underestimate the Chinese. Huawei was derided as a copycat and intellectual property thief for years before European operators eventually acknowledged it was designing superior network products to Ericsson and Nokia. DeepSeek stunned the world by apparently taking AI software to a new and more efficient level.

Nevertheless, it would obviously rankle Huawei's geopolitical foes to discover the Chinese company has beaten the US to an important semiconductor innovation. Chip design is the one field in which the US believes it still looks down on China from a lofty height. Restricting Huawei's and then China's access to semiconductors, as well as the tools and software needed to make them, therefore became America's main sanctions weapon. It would lose much of its sharpness if Her's Law is the breakthrough Huawei claims.

Update: This article has been amended since it was first published to indicate that He Tsingbo gave her speech in English, not Chinese. It also corrects a technical point: time scaling would not allow Huawei to produce 1.4-nanometer chips but essentially give it the equivalent processing output, the company says.

International Editor, Light Reading

Iain Morris joined Light Reading as News Editor at the start of 2015 -- and we mean, right at the start. His friends and family were still singing Auld Lang Syne as Iain started sourcing New Year's Eve UK mobile network congestion statistics. Prior to boosting Light Reading's UK-based editorial team numbers (he is based in London, south of the river), Iain was a successful freelance writer and editor who had been covering the telecoms sector for the past 15 years. His work has appeared in publications including The Economist (classy!) and The Observer, besides a variety of trade and business journals. He was previously the lead telecoms analyst for the Economist Intelligence Unit, and before that worked as a features editor at Telecommunications magazine. Iain started out in telecoms as an editor at consulting and market-research company Analysys (now Analysys Mason).

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